1. Field of the Invention
This invention relates to semiconductor storage devices equipped with test circuits that perform burn-in tests on memory cells and redundancy cells.
This application is based on patent application No. Hei 11-57576 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
Normally, in order to eliminate initial failures of semiconductor storage devices being manufactured, acceleration tests are performed by applying high voltages (hereafter, referred to as "stresses") to the semiconductor storage devices under high-temperature conditions. That is, so-called "burn-in" tests correspond to the tests in which stresses are applied to the semiconductor storage devices under the aforementioned high-temperature conditions to eliminate the initial failures.
Conventionally, during the burn-in tests, the semiconductor storage device is subjected to a burn-in test mode. Herein, pre-decoders are directly controlled so that word lines of plenty of memory cells are collectively selected, and stresses are imparted to the memory cells. In order to impart stresses to all of the memory cells during a predetermined time or more, all the word lines are selected sequentially or collectively so that an acceleration test time will be reduced.
Now, a description will be given with respect to an example of the semiconductor storage device in accordance with "related art 1" with reference to FIG. 6. Herein, after a redundancy circuit is activated, a burn-in test is performed by sequentially selecting all word lines being used in turn.
Operations of the burn-in test will be simply described below.
In FIG. 6, an address buffer 61 is supplied with an address signal ADRS, which is given from an external system or device (hereinafter, simply referred to as "external"). The address buffer 61 converts the address signal ADRS to an internal address signal AD, which is delivered to some internal circuits, namely, a row redundancy select circuit 63, a row decoder 64 and a column decoder 65.
The row decoder 64 decodes the internal address signal AD to produce a word line select signal WD, which selects one of the word lines. The word line select signal WD is supplied to corresponding memory cells within a normal memory cell area 67.
The row decoder 64 inputs a control signal RDE from the row redundancy select circuit 63. Herein, if the control signal RDE is in a High level, for example, the row decoder 64 does not output the word line select signal WD. That is, the row decoder 64 does not select the normal memory cell 67 because of a reason, as follows:
When a failure occurs on a memory cell connected with a word line being designated by the address signal ADRS, the row redundancy select circuit 63 operates so that the control signal RDE is set at the High level and is supplied to the row decoder 64.
The column decoder 65 decodes the internal address signal AD to produce a column select signal CSL to select one of bit lines. The column select signal CSL is supplied to a column selector 68. The normal memory cell area 67 is an area (or region) in which memory cells being subjected to normal addressing are formed.
In the normal memory cell area 67, the aforementioned word line select signal WD having the High level activates a number of memory cells, from which multiple sets of stored information "MD" are read out.
The column select signal CSL selects one of the multiple sets of the stored information MD. At a read mode, the column selector 68 deals read data as data DT, which are forwarded to portions of prescribed bits within an input/output buffer 69. At a write mode, the column selector 68 inputs data DT as write data from portions of prescribed bits within the input/output buffer 69.
At the read mode, the input/output buffer 69 amplifies the data DT to produce an output signal, which is output to a data terminal DATA. At the write mode, the input/output buffer 69 inputs the data DT as input signals from the data terminal DATA. So, the input/output buffer 69 amplifies the input signals, which are then supplied to the column selector 68. A test mode setting circuit 62 produces a test signal T1 based on a control signal being input from the external by way of an input terminal TEST. The test signal T1 is supplied to the row redundancy select circuit 63.
The row redundancy select circuit 63 selects one of redundancy word lines, being respectively connected with redundancy cells in a row redundancy cell area 66, on the basis of the internal address signal AD.
Next, the row redundancy select circuit 63 will be described in further detail with reference to FIG. 7.
In FIG. 7, the row redundancy select circuit 63 is configured using row redundancy address setting circuits 70.sub.0 to 70.sub.m (where "m" is an integer arbitrarily selected) and a row redundancy test decoder 72, by which redundancy word lines are to be selected in the row redundancy cell area 66.
Each of the row redundancy address setting circuits 70.sub.0 to 70.sub.m stores an address of a word line being connected with a "defective" memory cell in the normal memory cell area 67. When the row redundancy address setting circuits 70.sub.0 to 70.sub.m input addresses respectively stored therein, they output redundancy word signals RD.sub.0 to RD.sub.m by way of inverters 71.sub.0 to 71.sub.m respectively. Herein, each of the inverters 71.sub.0, to 71.sub.m inverts polarity of an input signal thereof.
The row redundancy test decoder 71 is activated when inputting the test signal T1. So, the row redundancy test decoder 71 outputs redundancy word select signals RW.sub.0 to RW.sub.m on the basis of the internal address signals AD. A NOR circuit 73.sub.0 is a two-input logical circuit of "NOR". Herein, the NOR circuit 73.sub.0 outputs a signal WD.sub.0 of a Low level when at least one of the redundancy word signal RD.sub.0 and redundancy word select signal RW.sub.0 is in a High level.
Similarly, NOR circuits 73.sub.1 to 73.sub.m are two-input logical circuits of "NOR", which respectively output signals WD.sub.1 to WD.sub.m of Low levels when the redundancy word signals RD.sub.0 to RD.sub.m and/or the redundancy word select signals RW.sub.1 to RW.sub.m are in High levels.
Inverters 74.sub.0 to 74.sub.m respectively invert polarities of the input signals WD.sub.0 to WD.sub.m. At a burn-in test mode, each inverter transforms High-level voltage to conform with booster voltage VB. So, the inverters 74.sub.0 to 74.sub.m produce redundancy word line select signals RWD.sub.0 to RWD.sub.m respectively.
A NAND circuit 75 is a (m+1)-input logical circuit of "NAND", which produces a word line select inhibit signal RDE based on the signals WD.sub.0 to WD.sub.m output from the NOR circuits 73.sub.0 to 73.sub.m. Herein, if one of the redundancy word select signals RW.sub.0 to RWm becomes "Low", the NAND circuit 75 outputs the word line select inhibit signal RDE of a High level, which is to be supplied to the row decoder 64. In other words, when one of the redundancy word line select signals RWD.sub.0 to RWD.sub.m becomes High, the word line select inhibit signal RDE becomes Low, so that the row redundancy select circuit 63 inhibits activation of the row decoder 64. Thus, it inhibits the word lines of the normal memory cell area 67 from being selected.
Next, a description will be given with respect to the row redundancy address setting circuit 70.sub.0, as the representative of the row redundancy address setting circuits 70.sub.0 to 70.sub.m, with reference to FIG. 8. That is, FIG. 8 is a block diagram showing a configuration of the row redundancy address setting circuit 70.sub.0.
In FIG. 8, a reference symbol "MM" designates a p-channel MOS transistor (where "MOS" is an abbreviation for "Metal Oxide Semiconductor"), which is to be turned ON or OFF by a control signal PS. Prior to the internal address signal AD being input to the row redundancy address setting circuit 70.sub.0, the p-channel MOS transistor MM performs precharge to a line DT10 by the control signal PS having a Low level.
The aforementioned address signal ADRS being input to the address buffer 61 consists of a number of address signals A.sub.0 to A.sub.n (where "n" is an integer), for example.
Based on the address signals A0 to An, the address buffer 61 produces and outputs internal address signals AD.sub.0 to AD.sub.n, and internal address signals AD.sub.0 B to AD.sub.n B respectively.
In response to the above signals, there are provided n-channel MOS transistors M.sub.0 to Mn and n-channel MOS transistors M.sub.0 B to M.sub.n B. As for the n-channel MOS transistor M.sub.0, a source is grounded, and a drain is connected to the line DT10 by way of a fuse resistor H.sub.0. In addition, the internal address signal AD.sub.0 is input to a gate of the n-channel MOS transistor Mo. When the internal address signal AD.sub.0 is in a High level, the n-channel MOS transistor M.sub.0 is ON, so that the line DT10 is discharged in electricity by way of the fuse resistor H.sub.0.
As for the n-channel MOS transistor M.sub.0 B, a source is grounded, and a drain is connected to the line DT10 by way of a fuse resistor H.sub.0 B. In addition, the internal address signal AD.sub.0 B is input to a gate of the n-channel MOS transistor M.sub.0 B. When the internal address signal AD.sub.0 B is in a High level, the n-channel MOS transistor M.sub.0 B is ON, so that the line DT10 is discharged in electricity by way of the fuse resistor H.sub.0 B.
Each of the n-channel MOS transistors M.sub.1 to M.sub.n is installed as similar to the aforementioned n-channel MOS transistor M.sub.0. That is, sources are grounded, and drains are connected to the line DT10 by way of fuse resistors H.sub.1 to H.sub.n respectively. In addition, the internal address signals Ad.sub.1 to Ad.sub.n are respectively input to gates of the n-channel MOS transistors M.sub.1 to M.sub.n. When the internal address signals Ad.sub.1 to Ad.sub.n become High, the n-channel MOS transistors M.sub.1 to M.sub.n, are ON respectively, so that the line DT10 is discharged in electricity by way of the fuse resistors H.sub.1 to H.sub.n respectively.
Each of the n-channel MOS transistors M.sub.n,B to M.sub.n B is installed as similar to the aforementioned n-channel MOS transistor M.sub.0 B. That is, sources are grounded, and drains are connected to the line DT10 by way of fuse resistors H.sub.1 B to H.sub.n B respectively. In addition, the internal address signals AD.sub.1 B to AD.sub.n B are respectively input to gates of the n-channel MOS transistors M.sub.1 B to M.sub.n B. When the internal address signals Ad.sub.1 B to Ad.sub.n B become High, the n-channel MOS transistors M.sub.1 B to M.sub.n B are ON respectively, so that the line DT10 is discharged in electricity by way of the fuse resistors H.sub.1 B to H.sub.n B respectively.
To store an address designating a word line connected with a defective memory cell in the normal memory cell area 67, disconnection is made on at least one of the fuse resistors H.sub.1 to H.sub.n and H.sub.1 B to H.sub.n B, which corresponds to a value inverse to polarity of the internal address signal AD.
Suppose that the internal address signals AD.sub.0, AD.sub.0 B, AD.sub.1 and AD.sub.1 B are respectively in High, Low, Low and High levels. In that case, the fuse resistors H.sub.0 B and H.sub.1 are disconnected. As described above, by disconnecting the fuse resistor corresponding to a value inverse to polarity of the internal address signal AD, the row redundancy address setting circuit 70.sub.0 stores the address designating the word line connected with the defective memory cell in the normal memory cell area 67.
When the row redundancy address setting circuit 70.sub.0 inputs data representative of the stored address designating the word line connected with the defective memory cell in the normal memory cell area 67, the line DT10 is at a High level because a discharge path disappears, so that an inverter 80 provides a Low-level output.
Next, the row redundancy test decoder 72 will be described in detail with reference to FIG. 9. FIG. 9 is a block diagram showing a configuration of the row redundancy test decoder 72.
The row redundancy test decoder 72 performs selection of memory cells with respect to the row redundancy cell area 66 (see FIG. 6), which has four word lines, for example. That is, the row redundancy test decoder 72 will be described under a prescribed condition where m=4.
In FIG. 9, reference numerals 82, 83 designate inverters, which invert polarities of the internal address signals AD.sub.0, Ad.sub.1 respectively. In addition, reference numerals 84-87 designate three-input AND circuits, each of which performs an logical operation of "AND" on an input signal thereof. For example, if the test signal T1 is High while both of the internal address signals AD.sub.0, Ad.sub.1 are High, the AND circuit 87 outputs a High level for the redundancy word select signal RW.sub.0.
Namely, the row redundancy test decoder 72 is activated by the test signal T1 so as to activate a specific word line of row redundancy cells, regardless of the setting of the row redundancy address setting circuits 70.sub.0 to 70.sub.m. Therefore, the row redundancy test decoder 72 is used for performing an operation test on memory cells of the row redundancy cell area 66.
According to the aforementioned operations of the circuits, a prescribed word line is selected based on the address signal ADRS being given from the external at a burn-in test mode, so that booster voltage VB is applied to memory cells connected with the selected word line.
When the address buffer 61 inputs an address signal ADRS representative of a word line which is not connected with a defective memory cell, the row decoder 64 selects a word line of the normal memory cell area 67, so that the booster voltage VB is applied to memory cells connected with the selected word line. When the address buffer 61 inputs an address signal ADRS representative of a word line which is connected with the defective memory cell, the present device inhibits word lines of the normal memory cell area 67 from being selected, but the row redundancy select circuit 63 selects a redundancy word line of the row redundancy cell area 66, so that the booster voltage VB is applied to memory cells connected with the selected redundancy word line.
Japanese Patent Application, First Publication No. Hei 9-63273 discloses another example of the semiconductor storage device as "related art 2", in which to reduce a burn-in test time, booster voltage is applied simultaneously to multiple word lines of the normal memory cell area.
Japanese Patent Application, First Publication No. Hei 9-45097 discloses a further example of the semiconductor storage device as "related art 3", in which at a burn-in test mode, multiple redundancy word lines are selected in addition to selecting the multiple word lines of the normal memory cell area. That is, the aforementioned configuration of the row redundancy address setting circuit (e.g., 70.sub.0, see FIG. 8) of the related art 1 is modified as shown in FIG. 10, wherein a p-channel MOS transistor M100 is inserted between power source and a line DT100. The p-channel MOS transistor M100 operates such that the line DT100, corresponding to the redundancy word line which is not selected, is discharged in electricity to a Low level at the burn-in test mode.
In FIG. 10, a test signal T4 representative of a burn-in test is input to a gate of the p-channel MOS transistor M100 by way of an inverter 81. When the test signal T4 is in a High level to designate a burn-in test mode, the p-channel MOS transistor M100 is turned ON.
At the burn-in test mode, any one of the n-channel MOS transistors M.sub.0 to M.sub.n and n-channel MOS transistors M.sub.0 B to M.sub.n B is ON, while the p-channel MOS transistor M100 is turned ON to prevent the line DT100 from being discharged by way of the fuse resistor. Thus, it is possible to avoid potential reduction of the line DT100.
For the reasons described above, the p-channel MOS transistor M100 needs a capability that allows currents to flow to maintain voltage of the line DT100 although the currents flow by way of the fuse resistors when all of the n-channel MOS transistors M.sub.0 to M.sub.n and n-channel MOS transistors M.sub.0 B to M.sub.n B are turned ON.
Japanese Patent Application No. Hei 3-515818 (corresponding to International Publication No. WO 92/06475) discloses a still further example of the semiconductor storage device (or semiconductor memory) as "related art 4", which is shown in FIG. 11. The semiconductor storage device of FIG. 11 provides a word line select circuit 151, a defective address storing circuit 155 (corresponding to the foregoing fuse resistors) and a control circuit 156 independently of the row decoder 158 (corresponding to the foregoing row decoder 64 shown in FIG. 6). Herein, this device is designed to simultaneously select word lines of normal memory cells and redundancy word lines of redundancy memory cells.
At a burn-in test mode, the word line select circuit 151 applies booster voltage to multiple word lines on the basis of a test mode signal being input to the control circuit 156. To reduce a leak current, the booster voltage is prevented from being applied to a word line whose address is stored in the defective address storing circuit 155.
The aforementioned related arts 1 to 4 suffer from problems as follows:
(1) Problem of Related Art 1
The semiconductor storage device of the related art 1 is designed such that by sequentially changing the address signals ADRS being given from the external, booster voltage can be applied sequentially to all of memory cells being used, such as normal memory cells and row redundancy memory cells. However, increasing memory capacities bring a remarkable increase in the burn-in test time, so the related art 1 suffers from a problem in which excessive times are needed in manufacture of the semiconductor storage devices.
(2) Problem of Related Art 2
The related art 2 describes selection of multiple word lines of normal memory cells, however, it lacks description with regard to configurations for selecting redundancy word lines of row redundancy cells. So, selecting the redundancy word lines of the row redundancy cells inhibit the row decoder from operating due to some signal which is equivalent to the aforementioned control signal RDE of the related art 1 for inhibiting word lines from being selected. That is, it becomes impossible to select the word lines of the normal memory cells.
As similar to the related art 1, there is a problem in which the related art 2 is incapable of performing the burn-in test by simultaneously selecting the word lines of the normal memory cells and the redundancy word lines of the row redundancy cells.
(3) Problem of Related Art 3
To solve the drawback in which the burn-in test cannot be performed by simultaneous selecting the word lines of the normal memory cells and the redundancy word lines of the row redundancy cells, the related art 3 is equipped with the p-channel MOS transistor M100 to retain potential of the line DT10 in a High level, by which the redundancy word lines are forced to be selected.
However, in order to provide the p-channel MOS transistor M100 with a sufficient current supply capability, it is increased in a formation area. This brings an increase in a chip area size as a whole. In addition, it allows excessive currents to flow. That is, the related art 3 suffers from a problem in which electric currents being consumed are increased.
In addition, there is a limit in the current supply capability as a test device. Thus, increasing the consumed currents so much will limit a number of semiconductor storage devices which can be collectively subjected to a burn-in test. That is, there is a problem in which the burn-in test requires a great amount of time in total.
(4) Problem of Related Art 4
The related art 4 needs defective address storing circuits (55) for storing defective addresses, each of which is used to check each of the words lines of the normal memory cells, so that booster voltage is applied to the checked word lines in the burn-in test. For this reason, the related art 4 needs an area for formation of the above circuits. So, there is a problem in which a chip area size is increased.